1. Field of the Invention
This invention relates generally to an Emitter-Coupled-Logic (ECL) to Transistor-Transistor-Logic (TTL) voltage level translator and, more particularly, to a circuit that translates an input voltage referenced to an ECL supply voltage V.sub.CC to a voltage referenced to a TTL supply voltage V.sub.EE independent of power supply voltage variations.
2. Background Art
The TTL and ECL logic families are commonly found in circuits designed in recent years. It is generally understood that circuits of the ECL family are referenced to the "top" supply voltage V.sub.CC and circuits of the TTL family are referenced to the "bottom" supply voltage V.sub.EE. Numerous requirements, such as mixed integrated logic, memory circuits, and system translator circuits, prompt the need to translate a signal referenced on supply voltage V.sub.CC to a signal referenced on supply voltage V.sub.EE. It would be desirable to have this translation occur over the full range of V.sub.EE variations.
One previously known circuit, described more fully in the Detailed Description of the Invention and FIG. 1, comprises an input means connected to a first supply voltage terminal for receiving supply voltage V.sub.CC, coupled for receiving an input signal referenced to supply voltage V.sub.CC, and having a first and second differential output connected to a base of a first and second NPN transistor, respectively. The emitter of the first NPN transistor is coupled to a current mirror circuit by a first resistor. The emitter of the second NPN transistor is coupled to the current mirror circuit by a second resistor. The first and second resistors have equal resistance. The current mirror is connected to a second supply voltage terminal for receiving supply voltage V.sub.EE. An emitter follower transistor has a base connected to a node between the second resistor and the current mirror and provides an output signal that is referenced to supply voltage V.sub.EE. However, the current mirror portion of the circuit requires a differential input and is slow to perform the translation because of the resistive-capacitive time constant associated with the first and second resistors and the Miller capacitance of a transistor in the current mirror.
Thus, an improved ECL to TTL voltage level translator is needed having a single input to the current mirror and that provides a faster translation time.